Overview

gnetlist is the gEDA netlister. It takes as input schematic files and produces a netlist. A netlist is a textual representation of a schematic. This textual representation has all of the connections between devices completely resolved. This means that all the connections associated with a net are grouped together. The netlister also handles hierarchies of schematics.

gnetlist has a very flexible architecture. The main program, which is written in C, reads in a schematic (using routines from libgeda) and creates an internal representation of the schematic data. This internal representation is then manipulated by a backend which is responsible for writing the various netlist formats. The backend for each netlist format is written in scheme (specifically Guile). This architecture not only allows for an infinite number of netlist formats, but also allows the netlister to generate other reports (like bill of material lists).

As of 20001006 gnetlist has scheme backends to support the following netlist formats:

  1. PCB & PCBboard - UNIX PCB netlist format.
  2. Allegro netlist format
  3. BAE netlist format
  4. BOM & BOM2 - Bill of Material generators
  5. DRC - Start of a design rule checker
  6. gEDA - the native format of gEDA, mainly used for testing
  7. Gossip netlist format
  8. PADS netlist format
  9. ProtelII netlist format
  10. Spice compatible netlist format
  11. Tango netlist format
  12. Verilog code
  13. VHDL code
  14. VIPEC netlist format
  15. VAMS - VHDL-AMS netlist format

This list is constantly growing. Several lacking features (as of 20001006) are: no support for buses, error detection and reporting is fairly limited, and ... (many more).

Ales Hvezda 2005-03-15